1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic RAM.
2. Description of the Related Art
In general, the data readout operation in a DRAM is effected by first selecting a memory cell, amplifying a minute potential difference occurring at this time between a pair of bit lines by means of a sense amplifier circuit, and then transferring the potential difference between the bit lines to a pair of data lines after the logic value "1" or "0" of the data is determined. Recently, the integration technology for DRAM has greatly advanced. With the advance in the integration technology, a parasitic capacitance between the pair of bit lines and a semiconductor substrate tends to increase and a memory cell capacitance tends to decrease. Therefore, it will take a long time to complete the sense amplifying operation of the sense amplifier circuit. Various attempts have been made to provide a circuit which can reduce the time.
FIG. 1 shows part of a circuit of the conventional DRAM. In the DRAM, barrier circuit 60 is connected between a pair of first bit lines BL1, BL1 and a pair of second bit lines BL2, BL2, switching circuit 63 is connected between second bit lines BL2, BL2 and a pair of data lines DQ, DQ, and sense amplifier circuit SA is connected between second bit lines BL2 and BL2.
Sense amplifier circuit SA includes first and second amplifier 61 and 62.
Barrier circuit 60 includes transistors T60 and T61, and barrier control signal .PHI.T is supplied to the gates of transistors T60 and T61. Transistors T60 and T61 are set in such conduction states as to serve as resistors in a latching process, and serve as good conductors in a restore process.
In the actual data readout operation, each of transistors T60 and T61 is first set in such a conduction state as to serve as a resistor. Then, data is read out from memory cell array 70 to the pair of bit lines BL1 and BL1. At this time, bit lines BL1 and BL1 are set at different potentials in accordance with the readout data. The potential difference is transmitted to bit lines BL2 and BL2 via transistors T60 and T61. The potential difference between bit lines BL2 and BL2 is sensed and amplified by sense amplifier circuit SA. Second amplifier 62 sets the potential of one of bit lines BL2 and BL2 to "VSS" level, and first amplifier 61 sets the potential of the other one of bit lines BL2 and BL2 to "VVD" level. After the potential change in each of bit lines BL2 and BL2 have almost completed, transistors T68 and T69 are set conductive. The potentials of data lines DQ and DQ are set to equivalent levels to respective bit lines BL2 and BL2 as data "0" or "1". Then, transistors T60 and T61 are set fully conductive to effect the restore process. At this time, the potentials of bit lines BL2 and BL2 are transmitted to bit lines BL1 and BL1 through barrier circuit 60 to store the same data as readout data or in memory cell array 70.
As described above, in the case where barrier circuit 60 which has transistors T60 and T61 serving as resistors in the latching process is provided, variation in potentials of second bit lines BL2 and BL2 having a small parasitic capacitance can be sensed and amplified in a relatively short period of time.
However, the conventional DRAM has the following defects:
In order to reduce the time required for completing the sense amplifying operation in which variation in potentials of second bit lines BL2 and BL2 is sensed and amplified, it is preferable that transistors T60 and T61 have large resistances in the latching process. However, if the resistances are set relatively large, it takes a long time to transmit a minute potential difference between bit lines BL1 and BL1, which is derived from a memory cell, to second bit lines BL2 and BL2.
Further, if transistors T60 and T61 are set nonconductive in the latching process, time for effecting the restore process becomes considerably long.
It is possible to reduce the time for effecting the latching process by enhancing the current driving ability of sense amplifier circuit SA. However, in this case, current consumption in the DRAM is liable to abruptly vary. Power source terminals P1 and P2 of the DRAM are respectively connected to voltage sources VCC and VSS via parasitic resistors RCC and RSS (see FIG. 3). Assume that current flowing into power source terminal P1 of the DRAM is denoted by ICC and current flowing out from power source terminal P2 of the DRAM is denoted by ISS. Then, the potential at power source terminal P1 is set to (VCC-ICC.times.RCC) and the potential at power source terminal P2 is set to (VSS+ISS.times.RSS). Therefore, when the current consumption abruptly varies, the values of ICC and ISS increase, causing a potential occurring in the DRAM to be shifted from the original value.
The DRAM is connected to receive external signals such as row address control signal RAS, column address control signal CAS, write control signal WE, and address signals A0 to A7 irrespective of the above potential shift. Therefore, the DRAM operation becomes unstable and erroneous operation may easily occur.